Ceramic chip carriers have conductive pads on one surface that extend around the edges of the chip carrier and as conductive coating into respective grooves in the sides thereof. An integrated circuit chip or die is bonded onto a central cavity area of the ceramic chip carrier and very small diameter wires are connected between the pads of the chip and the chip carrier. Top ends of electrical terminal posts in a dielectric frame of a chip carrier connector are soldered to the conductive coatings in the respective side grooves forming a terminated chip carrier package. The bottom ends of the terminal posts are then inserted into respective holes in a printed circuit board and flow soldered to conductive paths on the printed circuit board thereby electrically connecting the conductive paths to the terminal posts. The terminal posts are large in number, are in a square or rectangular pattern, and are spaced very closely together. The bottom ends of the terminal posts are typically misaligned with the respective holes which makes it difficult to insert them into the holes because of their large number, close spacing, lengths, and other factors that cause them to be out of alignment.